The semiconductor industry continues to yield integrated circuits (ICs) of increasing density in order to reduce their overall required chip space. At the same time, logic circuits continue to increase in speed, via a combination of higher component switching and pipelining techniques that increase the data throughput.
Integrated circuits are commonly implemented using dynamic logic. In dynamic logic, logic components are clocked by a clock signal, and communicate (i.e., transfer data) via dynamic busses. A standard dynamic bus normally operates in accordance with a clock signal CK, illustrated in FIG. 1. Clock signal CK has two timing phases--an evaluate phase CK1 and a precharge phase CK2. Components connected to the bus are precharged during precharge phase CK2 and evaluate during evaluate phase CK1. This type of bus is known generally as a single-phase dynamic bus. As the name implies, single-phase dynamic busses require that all components connected to the bus precharge and evaluate during identical phases. Accordingly, the actual bandwidth of the bus in relation to the overall bandwidth is reduced in proportion to the portion (typically 50%) of the duty cycle attributable to the precharge phase.
Recently, a bi-phase, single-bit dynamic bus implemented using a single wire has been developed, and is described in co-pending U.S. patent application Ser. No. 09/167,032, entitled "A Bi-Phase Single-Wire Dynamic Bus" to Meneghini et al., which is incorporated herein by reference. In accordance with the bi-phase single-wire dynamic bus, precharging and evaluation may occur on either phase of the clock signal. Precharging of the bus always occurs during the immediately subsequent clock phase of those clock phases during which the bus gets discharged. Thus, the precharger required for the bi-phase single-wire dynamic bus cannot rely simply on the current phase of the clock signal to determine whether or not to precharge the bus. Instead, the precharger must have some intelligence to know when the bus was discharged and to precharge the bus on the subsequent phase.
Accordingly, a need exists for an autonomous intelligent precharger circuit that monitors a dynamic bus, detects a discharge event on the bus, and automatically precharges the bus on the subsequent clock phase.